This invention relates to a serial to parallel conversion apparatus.
For example, a video signal of three primary colors of R (red), G (green) and B (blue) is sometimes transmitted as serial data over a monitor cable of copper lines and then converted into parallel data by a receiver.
In this instance, the receiver has a serial to parallel conversion apparatus incorporated therein for converting serial data into parallel data.
A serial to parallel conversion apparatus of the type mentioned detects word boundary indication data which is a reserved word of a special bit train which is intermittently included in inputted serial data and indicates a boundary position of a word, delimits the serial data at a correct word boundary in accordance with a result of the detection, converts the delimited serial data into parallel data and outputs the parallel data.
FIG. 7 is a block diagram of an exemplary one of conventional serial to parallel conversion apparatus.
Referring to FIG. 7, the serial to parallel conversion apparatus denoted at 1 includes an K-bit shift resister 2, a serial to parallel converter 3, a divider 4 for dividing a clock signal CLK into N, and a detector 5.
In the serial to parallel conversion apparatus 1, serial data SD of 1 bit are inputted to the shift register 2 in response to the clock signal CLK, and the thus inputted SD are stored by the shift register 2 and successively shifted in K flip-flops 2a.sub.1 to 2a.sub.K which compose the shift register 2.
In the shifting operation, outputs of the flip-flops 2a.sub.1 to 2a.sub.K are monitored by the detector 5 so that it is determined whether or not the outputs represent word boundary indication data.
Then, if the detector 5 detects the word boundary indication data, then the divider 4 is cleared (reset), and then an N-divided clock signal S4 obtained by dividing the clock signal CLK into N by the divider 4 with reference to the timing at which the divider 4 is cleared is outputted to the serial to parallel converter 3. The serial to parallel converter 3 converts the serial data of N bits inputted from the shift register 2 into parallel data PD with reference to the N-divided clock signal S4 and outputs the parallel data PD.
FIG. 8 is a block diagram showing another exemplary one of conventional serial to parallel conversion apparatus.
Referring to FIG. 8, the serial to conversion apparatus denoted at 11 includes N shift registers 12a.sub.1 to 12a.sub.N a serial to parallel converter 3, a divider 4 and a detector 15.
In 1:N serial to parallel conversion, word boundary indication data can possibly be detected at N different positions in accordance with an initial phase of the divider 4. In the serial to parallel conversion apparatus 11, an N-bit parallel signal S3 is inputted parallelly from the serial to parallel converter 3 to the N shift registers 12a.sub.1 to 12a.sub.N and is successively shifted in the shift registers 12a.sub.1 to 12a.sub.N. Then, the detector 15 detects a phase displacement between the word boundary indication data and the conversion processing of the serial to parallel converter 3 from the stored data of the shift registers 12a.sub.1 to 12a.sub.N and if a phase displacement is detected, then the phase of the divider 4 is modified.
However, the serial to parallel conversion apparatus 1 shown in FIG. 7 has a problem in that the detector 5 is required to detect in one period corresponding to the clock signal CLK whether or not the word boundary indication data is stored in the shift register 2 and it is difficult to design a detector to be used as the detector 5 so that it allows high speed processing.
Meanwhile, the serial to parallel conversion apparatus 11 shown in FIG. 8 has a different problem in that, where 1:N serial to parallel conversion is performed, there is the possibility that the word boundary indication data may be detected from N different positions and, in order to detect all of such data, a large integration scale is required for the circuit. The serial to parallel conversion apparatus 11 has another problem in that modifying the phase of the divider 4 in accordance with the detected position of the word boundary indication data is complicated and this complicates the circuit.